; Quartz frequency = 20,0 # Include list p = 16f873 __CONFIG _CP_ALL & _DEBUG_OFF & _WRT_ENABLE_ON & _CPD_OFF & _LVP_OFF & _BODEN_ON & _PWRTE_ON & _WDT_ON & _HS_OSC ; Controller configuration _CP_ALL-protection records of all banks; _CP_HALF; _CP_UPPER_256 errorlevel -302; not display the error to switch banks ;============================================================================================ ; CONSTANT K_ZAD equ D'60'; constant delay before conversion = 37mks ; REGISTERS cblock H'21' RF ; flags register RF = 1 - 0razryad-display one category, ; indicating two-1razryad razrd., 2razryad-display 3 digits ; UI ; temporary register to indicate UI1 ; Register-decimal value of under 1 bit on display UI2 ; Register-bit decimal value of 2 on display UI3 ; Register-decimal value of over 3 gap on display r_zad ; Register delay ADC cnt1 ; register for temporary storage delay cnt2 ; register for temporary storage delay cnt3 ; register for temporary storage delay endc ;============================================================================================== org 0 ; reset vector goto START ;----------------------------------------------------------------------- org 4 ; interrupt vector retfie ;----------------------------------------------------------------------- org H'10' segment clrf PCLATH ; conversion table DEC -> seven-segment code. addwf PCL, F dt 03F, 06, 05B, 04F, 066, 06D, 07D, 07, 07F, 06F ;----------------------------------------------------------------------- START ; Initialize processor registers bcf STATUS, RP0 ; Swap. on bank0 bcf STATUS, RP1 clrf PORTA ; Zeroing Port A clrf PORTB ; Zeroing Port B clrf PORTC ; Zeroing port C clrf CCP1CON ; Turn CCP module clrf TMR2 ; Clear TMR2 bsf STATUS, RP0 ; Swap. on bank1 movlw D'49' ; Set PWM period movwf PR2 bcf STATUS, RP0 ; Swap. on bank0 movlw D'24' ; Senior bits duty cycle movwf CCPR1L ; clrf INTCON ; Disable interrupt bsf STATUS, RP0 ; Swap. on bank1 movlw B'00001011' ; ports RA0, RA1, RA3 to enter, RA2, RA4, RA5-output movwf TRISA movlw B'00000000' ; Ports RB0-RB7, in the conclusion movwf TRISB movlw B'00000001' ; Ports RC1-RC7, at the conclusion RC0 to enter movwf TRISC clrf PIE1 clrf PIE2 movlw B'10000000' ; Nagruz.rez.porta B off, beat gener.na entrance WDT, predd.pered TMR0, koef.del = 1:1 movwf OPTION_REG movlw B'00000101' ; Left alignment, RA0/AN0, RA1/AN1, RA3/Vref, RA2, RA4, RA5-Digital movwf ADCON1 bcf STATUS, RP0 ; Swap. on bank0 clrf PIR1 ; Clear all peripheral interrupt flags movlw B'00001100' ; lower bits duty cycle = 00, PWM mode is set movwf CCP1CON movlw B'00000100' ; Coefficient prescaler TMR2 1:1; TMR2-enabled movwf T2CON movlw B'00000000' ; Coefficient prescaler TMR1-1:1, from internal Fosc / 4, TMR1-off movwf T1CON movlw b'00000001' ; Load sign indicating 1razryada in W movwf RF ; W load in the RF-register flags ;============================================================================================== CIKL clrwdt call ZAD_ADC ; Delay movlw B'10000001' ; establishes Fosc-32, incl. Feed on RA0/AN0, conversion for UN1 movwf ADCON0 call ZAD_ADC ; Delay bsf ADCON0, 2 ; Run ADC permit termination, R1 clrwdt btfsc ADCON0, 2 ; expect to complete the conversion from the ADC. Yes, jump over a step goto R1 movf ADRESH, w ; converted voltage from AN0 to write W call napr_sopr ; Perekodiruem tabular voltage resistance clrf PCLATH ; Zero the elder of the address register call B_D ; Binary BCD ; Output to display and set the order of display btfss RF, 0 ; check was 1 to 0 dis sensitive RF goto EX_UI1 ; NO-indication UI1 not derive bcf PORTC, 5 ; DA extinguish UI3 movf UI1, w ; load register UI1 -> W call segment ; Converting DEC -> in the seven-segment code andlw b'01111111' ; setting a mask for port B movwf PORTB ; output data in port B on the display bsf PORTC, 7 ; Ignites UI1 bcf RF, 0 ; Reset sign indicating a discharge bsf RF, 1 ; are established for the indication of 2 digits goto EX EX_UI1 btfss RF, 1 ; check was 1 to 1 of digits RF goto EX_UI2 ; NO-indication UI2 not derive bcf PORTC, 7 ; DA extinguish UI1 movf UI2, w ; load register UI2 -> W call segment ; Converting DEC -> in the seven-segment code andlw b'01111111' ; setting a mask for port B movwf PORTB ; output data in port B on the display bsf PORTB, 7 ; Set a comma bsf PORTC, 6 ; Ignites UI2 bcf RF, 1 ; Reset sign indicating 2 digits bsf RF, 2 ; are established for the display 3 digits goto EX EX_UI2 btfss RF, 2 ; check was 1 in 2 RF discharge register goto EX ; NO-indication UI3 not derive bcf PORTC, 6 ; DA extinguish UI2 movf UI3, w ; load register UI3 -> W call segment ; Converting DEC -> in the seven-segment code andlw b'01111111' ; setting a mask for port B movwf PORTB ; output data in port B on the display bcf PORTB, 7 ; Harvesting comma bsf PORTC, 5 ; Ignites UI3 bcf RF, 2 ; Reset sign indicating 3 digits bsf RF, 0 ; install a sign indicating a discharge call zad_cikl EX goto CIKL ;============================================================================================== ZAD_ADC movlw K_ZAD ; Delay 37 ms movwf r_zad ZAD decfsz r_zad, f goto ZAD return ;============================================================================================== B_D ; routine Binary BCD movwf UI1 ; bin of w placed in UI1 ; Conversion program B_D_UI clrf UI2 ; reset UI2 clrf UI3 ; reset UI3 gtenth movlw .10 ; dec = 10 placed in the w subwf UI1, W ; difference of Contents UI1 registration and w is stored in w (if w = 1) or UI1 (if w = 0) btfss STATUS, C ; if C is in the register STATUS = 1 then jump STATUS = 0, then unconditional transition goto gtenth1 ; movwf UI1 ; w recorded in the UI1 incf UI2, F ; Contents Register UI2 +1 recorded in UI2 goto gtenth ; gtenth1 movlw .10 ; dec = 10 placed in the w subwf UI2, W ; difference of Contents UI2 registration and w is stored in w (if w = 1) or UI2 (if w = 0) btfss STATUS, C ; if C is in the register STATUS = 1 then jump STATUS = 0, then unconditional transition goto over ; movwf UI2 ; w brought in UI2 incf UI3, F ; Contents Register UI3 +1 recorded in UI3 goto gtenth1 over return ;============================================================================================== zad_cikl return ;============================================================================================== org H'1FE' ; Conversion Table voltage resistance napr_sopr bsf PCLATH, 1 addwf PCL, F dt 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF dt 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF dt 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF dt 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF dt 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF dt 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF dt 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF dt 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF dt 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF, 0FF dt 0FF, 0FF, 0FD, 0FA, 0F5, 0F0, 0EB, 0E6, 0E1, 0DC, 0D7, 0D2, 0CD, 0C8, 0C5, 0C2 dt 0BE, 0BB, 0B8, 0B4, 0B1, 0AF, 0AD, 0AA, 0A7, 0A5, 0A3, 0A0, 9D, 9B, 99, 96, 93 dt 91, 8F, 8C, 89, 87, 85, 82, 7F, 7D, 7B, 78, 75, 73, 71, 6E, 6C dt 6A, 68, 66, 64, 61, 5F, 5D, 5A, 58, 56, 54, 52, 50, 4E, 4C, 4A dt 48, 46, 45, 43, 41, 40, 3E, 3C, 3B, 39, 37, 35, 34, 32, 30, 2E dt 2C, 2A, 28, 26, 25, 23, 22, 20, 1F, 1E, 1D, 1C, 1A, 19, 17, 15 dt 14, 13, 12, 10, 0F, 0E, 0D, 0B, 0A, 09, 08, 07, 06, 05, 03, 00 ;============================================================================================== end